1. Field of the Invention
The present invention relates to a data transfer method, and, more particularly, to a system and method for data transfer between a direct memory access controller (DMAC) and an interface unit that has a wider bus width than the data bus width of the DMAC.
2. Description of the Related Art
Information apparatuses, such as personal computers and hard disk units, incorporate a small computer system interface (SCSI) unit and a DMAC provided between the SCSI unit and a memory device. Further, a SCSI protocol controller (SPC) for controlling the SCSI is provided between the SCSI unit and the DMAC. It is preferable that the bus width of this SPC be set to an integer multiple of the current bus width in consideration of the number of bits of transfer data, which is likely to be increased in the future. For example, an SPC capable of transferring 8-bit data and 16-bit data between the SCSI unit and the DMAC is used.
FIG. 1 shows a conventional data transfer system in a reading system of reading data from a memory 13. The reading system uses a DMAC 11, an SPC 21, two switch circuits 14 and 15 each incorporating eight switches (not shown), and a selector 16.
The DMAC 11 sends an address signal ADD to the memory 13 to read 8-bit data DA from the memory 13. The read data DA is output as data DMD on a DMA bus 12, which has a bus width of eight bits. The DMAC 11 further sends a read/write signal R/W to the switch circuits 14 and 15 and the SPC 21 and sends a select signal DS (see FIG. 2) to the selector 16.
The SPC 21 has eight upper data input terminals 23A connected to the DMA bus 12 via the respective eight switches of the switch circuit 14, eight lower data input terminals 23B, which are connected to the DMA bus 12 via the respective eight switches of the switch circuit 15, and an output terminal connected to the SCSI data bus, which has an 8-bit bus width. In response to the read/write signal R/W having a low (L) level, the switch circuits 14 and 15 are turned on to permit 8-bit data DMD on the DMA bus 12 to be transferred to the data input terminals 23A and 23B respectively.
The SPC 21 includes a data register 22, which comprises a plurality of upper data registers 22A and a plurality of lower data registers 22B, and a transfer control unit 23. The upper data registers 22A receive and temporarily store 8-bit data DMD via the upper data input terminals 23A. The lower data registers 22B receive and temporarily store 8-bit data DMD via the lower data input terminals 23B.
The selector 16 alternately sends an upper select signal UDS and a lower select signal LDS to the transfer control unit 23 in accordance with the select signal DS (see FIG. 2). In response to both the read/write signal R/W and the upper select signal UDS having Low (L) levels, the transfer control unit 23 controls the data register 22 in such a way as to store the transfer data DMD into the upper data registers 22A. In response to both the read/write signal R/W and the lower select signal LDS having L levels, the transfer control unit 23 controls the data register 22 in such a manner as to store the transfer data DMD into the lower data registers 22B. In this manner, the DMAC 11, which is designed for eight bits, can be used to transfer 16-bit read data to a SCSI 10 from the DMAC 11.
FIG. 3 shows a conventional data transfer system in a writing system for writing data into the memory 13. FIG. 4 is a time chart illustrating the write operation. This writing system uses the DMAC 11, the SPC 21, two selectors 16 and 17 and a switch circuit 18. The upper and lower data registers 22A and 22B are connected to the selector 17 via the upper and lower data output terminals 24A and 24B. In accordance with the upper and lower select signals UDS and the LDS output from the selector 16, the selector 17 alternately selects the upper and lower data output terminals 24A and 24B to supply 8-bit data from the selected output terminals to the switch circuit 18.
In response to the read/write signal R/W having a high (H) level and the upper select signal UDS having an L level, the transfer control unit 23 controls the data register 22 to store the data, supplied via the SCSI data bus from the SCSI 10, into the upper data registers 22A. The data stored in the registers 22A are transferred as data DMD to the DMAC 11 via the upper data output terminals 24A, the selector 17, the switch circuit 18 and the DMA bus 12.
In response to the read/write signal R/W having an H level and the lower select signal LDS having an L level, the transfer control unit 23 controls the data register 22 to store data into the lower data registers 22B. The data stored in the registers 22B are transferred as data DMD to the DMAC 11 via the lower data output terminals 24B, the selector 17, the switch circuit 18 and the DMA bus 12. In this manner, the DMAC 11 sends the address signal ADD to the memory 13 to write upper and lower data DMD, each consisting of eight bits. Accordingly, it is possible to transfer 16-bit write data to the DMAC 11 from the SCSI 10.
The use of the switch circuits 14 and 15, the selectors 16 and 17 and the switch circuit 18 to transfer 16-bit data between the SCSI 10 and the DMAC 11 increases the number of components and their occupying area on the system board. This inevitably leads to an increase in the cost of the transfer system and enlargement of the system.